1. Field of the Invention
The present invention relates to computer systems for managing the routing of data through computer networks, and more particularly to an architecture which uses caches and multiple data channels to improve performance in bridging, routing, and gateway internetwork functions between a plurality of different types of networks.
2. Related Art
Internetwork devices, such as bridges, routers, and gateways often cause a significant bottleneck in communicating data through networks. When a number of high speed networks are connected to a single internetwork device, the processing resources of the internetwork device can be easily overwhelmed.
Techniques for managing the large volumes of data in such internetwork devices have been developed. One technique is to provide a very large memory to accumulate in-coming data, while the internetwork processor executes time-consuming procedures, which may delay the internetwork processor in routing packets of in-coming data. However, for high-throughput systems, a very large memory can be quite expensive. Furthermore, contention between the packet transfers and accesses by the internetwork processor to the memory to retrieve code and data limit the effectiveness of increasing memory size or processor power.
One solution is to provide a shared memory for storing packets of I/O data which are in transit through the internetwork device. The shared memory connects to an I/O bus and a processor bus. The processor bus accommodates transfers of code and data between the processor and a processor memory. The I/O bus accommodates packets of data which are in transit across the internetwork device. In this way, overall throughput of the internetwork device is improved by segregating transfers of code and data between processor and memory from transfers of the network packets flowing through the internetwork device. See U.S. Pat. No. 5,483,640, entitled SYSTEM FOR MANAGING DATA FLOW AMONG DEVICES BY STORING DATA AND STRUCTURES NEEDED BY THE DEVICES AND TRANSFERRING CONFIGURATION INFORMATION FROM PROCESSOR TO THE DEVICES, by inventors Mark S. Isfeld and Bruce W. Mitchell.
U.S. Pat. No. 5,483,640 discloses a system which employs a small external cache for I/O data located near the shared memory to improve system performance. However, rapidly increasing processor clock speeds make the performance gains from such a small external cache marginal. In order to achieve an increase in system performance commensurate with the increase in processor clock speeds, it is necessary to move the I/O data directly from shared memory into a faster processor-controlled cache. However, maintaining copies of I/O data from the shared memory in an processor-controlled cache can create consistency problems. If a copy of an item of I/O data is modified in the processor-controlled cache, the internetwork system must ensure that accesses to the unmodified version in the shared memory do not proceed until the modified version in the processor-controlled cache is copied back to the shared memory. This operation is commonly referred to as a flush. Conversely, when an item of I/O data is modified in the shared memory by an I/O device, the system must ensure that a copy of the item of I/O data inside the processor-controlled cache is either updated or invalidated.
In this way, a form of consistency known as coherency can be maintained between items of I/O data in the shared memory and copies of these items of I/O data in the processor-controlled cache through communications across the processor bus. However, this consistency traffic across the processor bus increases the load on the processor bus. This undercuts the purpose of separating the processor bus from the I/O bus in the first place, which is to reduce contention in the processor-to-memory data channel.
What is needed is a structure to enforce consistency rules between items of data in the shared memory and copies of these items of data in an processor-controlled cache while minimizing consistency traffic across the processor bus.